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| (R) ISL28133, ISL28233, ISL28433 Data Sheet May 29, 2009 FN6560.1 Single, Dual, and Quad Micropower, Zero-Drift, RRIO Operational Amplifiers The ISL28133, ISL28233 are single and dual micropower, zero-drift operational amplifiers that are optimized for single supply operation from 1.65V to 5.5V. Their low supply current of 18A and wide input range enable the ISL28133 to be an excellent general purpose op amp for a range of applications. The ISL28133 is ideal for handheld devices that operates off 2 AA or single Li-ion batteries. The ISL28133 is available in the 5 Ld SOT-23, the 5 Ld SC70 and the 6 Ld 1.6mmx1.6mm TDFN packages. All devices operates over the extended temperature range of -40C to +125C. Features * Low Input Offset Voltage . . . . . . . . . . . . . . . . . . 8V, Max. * Low Offset Drift. . . . . . . . . . . . . . . . . . . . 0.075V/C, Max * Quiescent Current . . . . . . . . . . . . . . . . . . . . . . 18A, Typ. * Wide Supply Range . . . . . . . . . . . . . . . . . . . 1.65V to 5.5V * Low Noise (0.01Hz to 10Hz). . . . . . . . . . . . . 1.1VP-P, Typ. * Rail-to-Rail Inputs and Output * Input Bias Current . . . . . . . . . . . . . . . . . . . . . 300pA, Max. * Operating Temperature Range. . . . . . . . . -40C to +125C Pinouts ISL28133 (5 LD SOT-23) TOP VIEW OUT V1 2 +3 4 IN5 V+ IN+ VIN- Ordering Information PART NUMBER ISL28133FHZ-T7* (Note 1) PART MARKING BCFA PACKAGE (Pb-Free) 5 Ld SOT-23 5 Ld SOT-23 5 Ld SC70 5 Ld SC70 6 Ld TDFN 8 Ld MSOP 8 Ld MSOP 8 Ld TDFN PKG. DWG. # MDP0038 ISL28133 (5 LD SC-70) TOP VIEW 1 + 4 OUT 8 V+ -+ +7 OUT_B 6 IN-_B 5 IN+_B 14 OUT_D -+ +13 IN-_D 12 IN+_D 11 V10 IN+_C -+ +9 IN-_C 8 OUT_C 2 3 5 V+ Coming Soon BCFA ISL28133FHZ-T7A* (Note 1) Coming Soon ISL28133FEZ-T7* (Note 1) BHA MDP0038 IN+ P5.049 P5.049 L6.1.6x1.6 MDP0043 MDP0043 TBD Coming Soon BHA ISL28133FEZ-T7A* (Note 1) Coming Soon T8 ISL28133FRUZ-T7* (Note 2) Coming Soon ISL28233FUZ (Note 1) Coming Soon ISL28233FUZ-T7* (Note 1) 8233Z 8233Z ISL28133 (6 LD TDFN) TOP VIEW OUT 1 V- 2 IN - 3 -+ 6 V+ 5 NC 4 IN + OUT_A 1 IN-_A 2 IN+_A 3 V- 4 ISL28233 (8 LD MSOP) TOP VIEW Coming Soon TBD ISL28233FRTZ-T7* (Note 1) Coming Soon ISL28433FVZ (Note 1) TBD 14 Ld TSSOP M14.173 ISL28233 (8 LD TDFN) TOP VIEW VOUT A -IN A +IN A V1 2 3 4 -+ +8 V+ 7 VOUT B 6 -IN B 5 +IN B OUT_A 1 IN-_A 2 IN+_A 3 V+ 4 IN+_B 5 IN-_B 6 OUT_B 7 *Please refer to TB347 for details on reel specifications. NOTES: 1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. ISL28433 (14 LD TSSOP) TOP VIEW 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL28133, ISL28233, ISL28433 Absolute Maximum Ratings Max Supply Voltage V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V Max Voltage VIN to GND . . . . . . . . . . . . . . . . . . . . . . -0.5V to 5.75V Max Input Differential Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.75V Max Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Max Voltage VOUT to GND (10s) . . . . . . . . . . . . . . . . . . . . . . 5.75V ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3000V Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . .1500V Thermal Information Thermal Resistance (Typical, Note 3) JA (C/W) 5 Ld SOT-23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 5 Ld SC70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 6 Ld TDFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +125C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25C, RL = 10k, unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C. DESCRIPTION CONDITIONS MIN (Note 4) TYP MAX (Note 4) UNIT PARAMETER DC SPECIFICATIONS VOS Input Offset Voltage -8 -15.5 2 8 15.5 V V V/C pA TCVOS IOS IB Input Offset Voltage Temperature Coefficient Input Offset Current Input Bias Current -300 -600 0.02 -60 30 0.075 300 600 5.1 pA pA V dB dB Common Mode Input Voltage Range CMRR Common Mode Rejection Ratio V+ = 5.0V, V- = GND VCM = -0.1V to 5.0V -0.1 118 115 125 PSRR Power Supply Rejection Ratio Vs = 2V to 5.5V 110 110 138 dB dB VOH VOL AOL V+ IS Output Voltage Swing, High Output Voltage Swing, Low Open Loop Gain Supply Voltage Supply Current RL = 10k 4.965 4.981 18 35 V mV dB 5.5 V A A mA mA RL = 1M (Note 5) RL = OPEN 1.65 200 18 25 35 ISC+ ISCAC SPECIFICATONS GBWP eN VP-P eN Output Source Short Circuit Current Output Sink Short Circuit Current RL = Short to ground or V+ 13 -26 17 -19 26 -13 Gain Bandwidth Product f = 50kHz Peak-to-Peak Input Noise Voltage Input Noise Voltage Density AV = 100, RF = 100k, RG = 1k, RL = 10k to VCM f = 0.01Hz to 10Hz f = 1kHz 400 1.1 65 kHz VP-P nV/(Hz) 2 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 Electrical Specifications V+ = 5V, V- = 0V, VCM = 2.5V, TA = +25C, RL = 10k, unless otherwise specified. Boldface limits apply over the operating temperature range, -40C to +125C. (Continued) DESCRIPTION Input Noise Current Density f = 1kHz f = 10Hz Cin Differential Input Capacitance Common Mode Input Capacitance TRANSIENT RESPONSE SR Positive Slew Rate Negative Slew Rate tr, tf, Small Signal Rise Time, tr 10% to 90% Fall Time, tf 10% to 90% tr, tf Large Signal Rise Time, tr 10% to 90% Fall Time, tf 10% to 90% ts NOTES: 4. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 5. Parts are 100% tested with a minimum operating voltage of 1.65V to a VOS limit of 15V. Settling Time to 0.1%, 2VP-P Step AV = +1, VOUT = 0.1VP-P, RF = 0, RL = 10k, CL = 1.2pF AV = +1, VOUT = 2VP-P, RF = 0, RL = 10k, CL = 1.2pF AV = +1, RF = 0, RL = 10k, CL = 1.2pF VOUT = 1V to 4V, RL = 10k 0.2 0.1 1.1 1.1 8 10 35 V/s V/s s s s s s f = 1MHz CONDITIONS MIN (Note 4) TYP 72 79 1.6 1.12 MAX (Note 4) UNIT fA/(Hz) fA/(Hz) pF pF PARAMETER iN Typical Performance Curves 200 OPEN LOOP GAIN (dB)/PHASE () 150 100 50 0 -50 RL = 10k CL = 100pF SIMULATION 10 GAIN V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. 200 OPEN LOOP GAIN (dB)/PHASE () 150 100 50 0 -50 RL = 10M CL = 100pF SIMULATION 10 100 1k 10k 100k 1M 10M GAIN PHASE PHASE -100 0.1m 1m 10m 100m 1 100 1k 10k 100k 1M 10M -100 0.1m 1m 10m 100m 1 FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 1. FREQUENCY RESPONSE vs OPEN LOOP GAIN, RL = 10k FIGURE 2. FREQUENCY RESPONSE vs OPEN LOOP GAIN, RL = 10M 3 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 Typical Performance Curves 2 1 NORMALIZED GAIN (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 100 V+ = 1.6V CL = 3.7pF AV = +1 VOUT = 10mVP-P 1k 10k 100k 1M 10M RL = 1k RL = 10k RL = 49.9k RL = 100k RL = OPEN NORMALIZED GAIN (dB) V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued) 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 100 V+ = 5V CL = 3.7pF AV = +1 VOUT = 10mVP-P 1k 10k 100k 1M 10M RL = 1k RL = 10k RL = 49.9k RL = OPEN RL = 100k FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 3. GAIN vs FREQUENCY vs RL, VS = 1.6V FIGURE 4. GAIN vs FREQUENCY vs RL, VS = 5V 10 NORMALIZED GAIN (dB) 9 NORMALIZED GAIN (dB) 8 7 6 5 4 3 2 1 V+ = 5V RL = 100k CL = 3.7pF AV = +2 VOUT = 10mVP-P 1k 10k FREQUENCY (Hz) 100k 1M Rf = Rg = 1k Rf = Rg = 100k Rf = Rg = 10k 1 0 -1 -2 -3 -4 -5 -6 V+ = 5V RL = OPEN -7 CL = 3.7pF -8 A = +1 V -9 1k 100 VOUT = 1V VOUT = 500mV VOUT = 250mV VOUT = 100mV VOUT = 10mV 0 100 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 5. GAIN vs FREQUENCY vs FEEDBACK RESISTOR VALUES Rf/Rg FIGURE 6. GAIN vs FREQUENCY vs VOUT, RL = OPEN 70 60 50 GAIN (dB) 40 30 20 10 0 AV = 1 Rg = OPEN, Rf = 0 100 1k 10k 100k FREQUENCY (Hz) 1M 10M AV = 10 Rg = 10k, Rf = 100k AV = 100 Rg = 1k, Rf = 100k V+ = 5V CL = 3.7pF RL = 100k VOUT = 10mVP-P AV = 1000 Rg = 100, Rf = 100k NORMALIZED GAIN (dB) 1 0 -1 -2 -3 -4 -5 -6 -7 -8 RL = 100k CL = 3.7pF AV = +1 VOUT = 10mVP-P 1k 10k 100k 1M 10M V+ = 1.2V V+ = 1.6V V+ = 3.0V V+ = 5.5V -10 10 -9 100 FREQUENCY (Hz) FIGURE 7. FREQUENCY RESPONSE vs CLOSED LOOP GAIN FIGURE 8. GAIN vs FREQUENCY vs SUPPLY VOLTAGE 4 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 Typical Performance Curves 8 6 NORMALIZED GAIN (dB) 4 2 0 -2 -4 -6 -8 V+ = 5V RL = 100k AV = +1 VOUT = 10mVP-P 1k CL = 824pF CL = 474pF CL = 224pF CMRR (dB) V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued) 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 1M 10M -100 10 100 1k 10k V+ = 5V RL = 100k CL = 16.3pF AV = +1 VCM = 1VP-P 100k 1M 10M CL = 104pF CL = 51pF CL = 3.7pF 10k 100k FREQUENCY (Hz) -10 100 FREQUENCY (Hz) FIGURE 9. GAIN vs FREQUENCY vs CL FIGURE 10. CMRR vs FREQUENCY, VS = 5V 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10 100 PSRR1k 10k 100k PSRR+ V+ = 5V RL = 100k CL = 16.3pF AV = +1 VCM = 1VP-P 1M 10M CMRR (dB) PSRR (dB) 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10 100 1k 10k 100k V+ =1.6V RL = 100k CL = 16.3pF AV = +1 VCM = 1VP-P 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 11. PSRR vs FREQUENCY, VS = 5V FIGURE 12. CMRR vs FREQUENCY, VS = 1.6V 0 -10 -20 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 10 100 1k 10k 100k PSRRPSRR+ V+ = 1.6V RL = 100k CL = 16.3pF AV = +1 VCM = 1VP-P 1M 10M 1000 INPUT NOISE VOLTAGE (nV/Hz) V+ = 5V AV = 1 100 10 0.001 0.01 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 13. PSRR vs FREQUENCY, VS = 1.6V FIGURE 14. INPUT NOISE VOLTAGE DENSITY vs FREQUENCY 5 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 Typical Performance Curves 1.0 INPUT NOISE CURRENT (pA/Hz) INPUT NOISE VOLTAGE (nV) V+ = 5V AV = 1 V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued) 800 600 400 200 0 -200 -400 -600 0 V+ = 5V RL = 100k CL = 3.7pF Rg = 10, Rf = 100k AV = 10,000 10 20 30 40 50 60 70 80 90 100 TIME (s) 0.1 0.01 0.001 0.01 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) FIGURE 15. INPUT NOISE CURRENT DENSITY vs FREQUENCY FIGURE 16. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz 5.0 4.5 4.0 LARGE SIGNAL (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 50 100 150 200 TIME (s) 250 300 350 400 V+ = 5V RL = 100k CL = 3.7pF AV = 1 VOUT = 4VP-P LARGE SIGNAL (V) 1.2 1.0 0.8 0.6 0.4 0.2 0 V+ = 5V RL = 100k CL = 3.7pF AV = 1 VOUT = 1VP-P 0 10 20 30 40 50 60 70 80 90 100 TIME (s) FIGURE 17. LARGE SIGNAL STEP RESPONSE (4V) FIGURE 18. LARGE SIGNAL STEP RESPONSE (1V) 0.14 0.12 SMALL SIGNAL (V) 0.10 0.08 0.06 0.04 0.02 0 0 5 10 15 20 TIME (s) 25 30 35 40 V+ = 5V RL = 100k CL = 3.7pF AV = 1 VOUT = 100mVP-P AVERAGE VOS (V) 3.5 N = 67 3.0 2.5 2.0 1.5 1.0 0.5 +125C 125C +25C -40C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) FIGURE 19. SMALL SIGNAL STEP RESPONSE (100mV) FIGURE 20. AVERAGE INPUT OFFSET VOLTAGE vs SUPPLY VOLTAGE 6 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 Typical Performance Curves 8 6 4 2 VOS (V) MIN VOS (uV) 0 -2 -4 -6 -8 -10 -12 -40 -20 0 20 40 60 80 100 120 4 2 0 -2 -4 MIN -6 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C) TEMPERATURE (C) MEDIAN MAX MEDIAN V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued) N = 67 10 8 6 MAX N = 67 FIGURE 21. VOS vs TEMPERATURE, VS = 1.0V, VIN = 0V, RL = INF FIGURE 22. VOS vs TEMPERATURE, VS = 2.5V,VIN = 0V, RL = INF 200 N = 12 150 IBIAS IN+(pA) IBIAS IN-(pA) +125C 100 250 200 150 100 50 0 -50 1.5 -40C +25C +100C +75C N = 12 +125C 50 +100C +75C -40C -40C +25C 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 -50 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) FIGURE 23. AVERAGE NON-INVERTING INPUT BIAS CURRENT vs SUPPLY VOLTAGE vs TEMPERATURE FIGURE 24. AVERAGE INVERTING INPUT BIAS CURRENT vs SUPPLY VOLTAGE vs TEMPERATURE 10 0 AVERAGE IOS (pA) -10 -40C CMRR (dB) -20 -30 -40 -50 -60 +125C +25C N = 67 200 N = 67 180 MAX 160 MEDIAN 140 120 100 MIN -70 -80 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 80 -40 -20 0 20 40 60 80 100 120 SUPPLY VOLTAGE (V) TEMPERATURE (C) FIGURE 25. IOS vs SUPPLY VOLTAGE vs TEMPERATURE FIGURE 26. CMRR vs TEMPERATURE, VCM = -2.5V TO +2.5V, V+ = 2.5V 7 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 Typical Performance Curves 155 N = 67 145 135 PSRR (dB) VOUT (V) 125 115 105 95 85 75 -40 -20 0 20 40 60 80 100 120 MIN MEDIAN MAX 4.984 4.982 4.980 MEDIAN 4.978 4.976 4.974 4.972 -40 MIN MAX V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued) 4.986 N = 67 -20 0 20 40 60 80 100 120 TEMPERATURE (C) TEMPERATURE (C) FIGURE 27. PSRR vs TEMPERATURE, V+ = 2V TO 5.5V FIGURE 28. VOUT HIGH vs TEMPERATURE, RL = 10k, VS +-2.5V 0.024 0.023 0.022 VOUT (V) 0.021 0.020 0.019 MIN 0.018 0.017 0.016 -40 MEDIAN MAX N = 67 AVERAGE SUPPLY CURRENT (A) 25 24 23 22 21 20 +25C 19 18 17 16 -20 0 20 40 60 80 100 120 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 TEMPERATURE (C) SUPPLY VOLTAGE (V) -40C N = 67 +125C FIGURE 29. VOUT LOW vs TEMPERATURE, RL = 10k, VS +-2.5V FIGURE 30. SUPPLY CURRENT vs SUPPLY VOLTAGE 28 N = 67 26 SUPPLY CURRENT (A) 24 22 20 18 16 14 -40 MEDIAN MIN SUPPLY CURRENT (A) MAX 30 28 26 24 22 20 MIN 18 16 -20 0 20 40 60 80 100 120 14 -40 -20 0 20 40 60 80 100 120 MEDIAN N = 67 MAX TEMPERATURE (C) TEMPERATURE (C) FIGURE 31. V+ SUPPLY CURRENT vs TEMPERATURE, VS = 0.8V, VIN = 0V, RL = INF FIGURE 32. V+ SUPPLY CURRENT vs TEMPERATURE, VS = 2.5V, VIN = 0V, RL = INF 8 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 Typical Performance Curves V+ = 5V, V- = 0V, VCM = 2.5V, RL = Open. (Continued) 32 30 SUPPLY CURRENT (A) 28 26 24 22 20 18 16 14 -40 -20 0 20 40 60 80 100 120 MAX MIN MEDIAN N = 67 TEMPERATURE (C) FIGURE 33. V+ SUPPLY CURRENT vs TEMPERATURE, VS = 3.0V, VIN = 0V, RL = INF Pin Descriptions n ISL28133 ISL28133 ISL28133 (5 Ld SOT23) (5 Ld SC70) (6 Ld TDFN) 3 1 4 ISL28233 (8 Ld MSOP, 8 Ld TDFN) 3(A) 5(B) ISL28433 PIN (14 Ld TSSOP) NAME FUNCTION 3(A) 5(B) 10(C) 12(D) IN+ Noninverting input IN+ EQUIVALENT CIRCUIT V+ + + INV- CLOCK GEN + DRIVERS Circuit 1 2 4 2 3 2 3 4 2(A) 6(B) 11 2(A) 6(B) 9(C) 13(D) 1(A) 7(B) 8(C) 14(D) VIN- Negative supply Inverting input (See Circuit 1) 1 4 1 1(A) 7(B) OUT Output V+ OUT VCircuit 2 5 5 6 5 8 4 V+ NC Positive supply Not connected Not internally connected 9 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 MAIN AMPLIFIER 5kHz CROSSOVER FILTER ININ+ VOUT CHOPPER STABILIZED DC OFFSET CORRECTION FIGURE 34. ISL28x33 FUNCTIONAL BLOCK DIAGRAM Applications Information Functional Description The ISL28133 uses a proprietary auto-zero architecture (Figure 34) that combines a 400kHz main amplifier with a very high open loop gain (200dB) chopper stabilized amplifier to achieve very low offset voltage and drift (2V, 0.02V/C typical) while consuming only 18A of supply current per channel. This multi-path amplifier architecture contains a time continuous main amplifier whose input DC offset is corrected by a parallel-connected, high gain chopper stabilized DC correction amplifier operating at 100kHz. From DC to ~5kHz, both amplifiers are active with DC offset correction and most of the low frequency gain is provided by the chopper amplifier. A 5kHz crossover filter cuts off the low frequency amplifier path leaving the main amplifier active out to the 400kHz gain-bandwidth product of the device. The key benefits of this architecture for precision applications are very high open loop gain, very low DC offset, and low 1/f noise. The noise is virtually flat across the frequency range from a few millihertz out to 100kHz, except for the narrow noise peak at the amplifier crossover frequency (5kHz). where either input is expected to exceed the rails by 0.5V, an external series resistor must be used to ensure the input currents never exceed 20mA (Figure 35). VIN RIN + RL VOUT FIGURE 35. INPUT CURRENT LIMITING Layout Guidelines for High Impedance Inputs To achieve the maximum performance of the high input impedance and low offset voltage of the ISL28X33 amplifiers, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. The use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 36 shows how the guard ring should be configured. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. By setting the guard ring voltage equal to the voltage at the non-inverting input, parasitic capacitance is minimized as well. HIGH IMPEDANCE INPUT IN + GUARD RING PC TRACE V+ ISL28133 Rail-to-rail Input and Output (RRIO) The RRIO CMOS amplifier uses parallel input PMOS and NMOS that enable the inputs to swing 100mV beyond either supply rail. The inverting and non-inverting inputs do not have back-to-back input clamp diodes and are capable of maintaining high input impedance at high differential input voltages. This is effective in eliminating output distortion caused by high slew-rate input signals. The output stage uses common source connected PMOS and NMOS devices to achieve rail-to-rail output drive capability with 17mA current limit and the capability to swing to within 20mV of either rail while driving a 10k load. FIGURE 36. USE OF GUARD RINGS TO REDUCE LEAKAGE High Gain, Precision DC Coupled Amplifier The circuit in Figure 37 implements a single-stage DC coupled amplifier with an input DC sensitivity of under 100nV that is only possible using a low VOS amplifier with high open loop gain. High gain DC amplifiers operating from low IN+ and IN- Protection All input terminals have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode beyond the supply rails. For applications 10 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 voltage supplies are not practical using typical low offset precision op amps. For example, the typical 100V VOS and offset drift 0.5V/C of a low offset op amp would produce a DC error of >1V with an additional 5mVC of temperature dependent error making it difficult to resolve DC input voltage changes in the micro-volt range. The 8V max VOS and 0.075V/C of the ISL28133 produces a temperature stable maximum DC output error of only 80mV with a maximum temperature drift of 0.75V/C. The additional benefit of a very low 1/f noise corner frequency and some feedback filtering enables DC voltages and voltage fluctuations well below 100nV to be easily detected with a simple single stage amplifier. CF 0.018F 1M, +2.5V VIN 100 1M ISL28133 + 100 -2.5V VOUT RL ISL28133 SPICE Model Figure 38 shows the SPICE model schematic and Figure 39 shows the net list for the ISL28133 SPICE model. The model is a simplified version of the actual device and simulates important parameters such as noise, Slew Rate, Gain and Phase. The model uses typical parameters from the ISL28133. The poles and zeros in the model were determined from the actual open and closed-loop gain and phase response. This enables the model to present an accurate AC representation of the actual device. The model is configured for ambient temperature of +25C. Figures 40 through 47 show the characterization vs simulation results for the Noise Density, Frequency Response vs Close Loop Gain, Gain vs Frequency vs CL and Large Signal Step Response (4V). ACL = 10kV/V FIGURE 37. HIGH GAIN, PRECISION DC COUPLED AMPLIFIER 11 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 V16 V15 Dn2 Dn1 I2 7 R22 + + - R21 I1 R1 R2 Vin+ En Cin1 M1 M2 Cin2 13 VinR3 R4 12 4 Voltage Noise Input Stage 7 + G2 V4 13 R6 D2 + G4 V6 R8 C1 D4 7 VV3 12 G1 R5 V3 D1 G3 R7 C2 D3 V5 16 - + 4 + 4 Gain Stage SR Limit & First Pole 7 + G5 R11 VV3 R12 L1 + G8 R14 C3 D7 D8 + G10 V+ R16 Vout 16 R10 E1 + + 4 G5 + R9 L2 G7 + R13 C4 G9 + D6 D5 G10 + G11 + R15 VZero/Pole Pole Output Stage FIGURE 38. SPICE CIRCUIT SCHEMATIC 12 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 * ISL28133 Macromodel * Revision B, April 2009 * AC characteristics, Voltage Noise * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | | | | | .subckt ISL28133 3 2 7 4 6 * *Voltage Noise D_DN1 102 101 DN D_DN2 104 103 DN R_R21 0 101 120k R_R22 0 103 120k E_EN 8 3 101 103 1 V_V15 102 0 0.1Vdc V_V16 104 0 0.1Vdc * *Input Stage C_Cin1 8 0 0.4p C_Cin2 2 0 2.0p R_R1 9 10 10 R_R2 10 11 10 R_R3 4 12 100 R_R4 4 13 100 M_M1 12 8 9 9 pmosisil + L=50u + W=50u M_M2 13 2 11 11 pmosisil + L=50u + W=50u I_I1 4 7 DC 92uA I_I2 7 10 DC 100uA * *Gain stage G_G1 4 VV2 13 12 0.0002 G_G2 7 VV2 13 12 0.0002 R_R5 4 VV2 1.3Meg R_R6 VV2 7 1.3Meg D_D1 4 14 DX D_D2 15 7 DX V_V3 VV2 14 0.7Vdc V_V4 15 VV2 0.7Vdc * *SR limit first pole G_G3 4 VV3 VV2 16 1 G_G4 7 VV3 VV2 16 1 R_R7 4 VV3 1meg R_R8 VV3 7 1meg C_C1 VV3 7 12u C_C2 4 VV3 12u D_D3 4 17 DX D_D4 18 7 DX V_V5 VV3 17 0.7Vdc V_V6 18 VV3 0.7Vdc * *Zero/Pole E_E1 16 4 7 4 0.5 G_G5 4 VV4 VV3 16 0.000001 G_G6 7 VV4 VV3 16 0.000001 L_L1 20 7 0.3H R_R12 20 7 2.5meg R_R11 VV4 20 1meg L_L2 4 19 0.3H R_R9 4 19 2.5meg R_R10 19 VV4 1meg *Pole G_G7 4 VV5 VV4 16 0.000001 G_G8 7 VV5 VV4 16 0.000001 C_C3 VV5 7 0.12p C_C4 4 VV5 0.12p R_R13 4 VV5 1meg R_R14 VV5 7 1meg * *Output Stage G_G9 21 4 6 VV5 0.0000125 G_G10 22 4 VV5 6 0.0000125 D_D5 4 21 DY D_D6 4 22 DY D_D7 7 21 DX D_D8 7 22 DX R_R15 4 6 8k R_R16 6 7 8k G_G11 6 4 VV5 4 -0.000125 G_G12 7 6 7 VV5 -0.000125 * .model pmosisil pmos (kp=16e-3 vto=10m) .model DN D(KF=6.4E-16 AF=1) .MODEL DX D(IS=1E-18 Rs=1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28133 FIGURE 39. SPICE NET LIST 13 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 v Characterization vs Simulation Results INPUT NOISE VOLTAGE (nV/ Hz V+ = 5V AV = 1 INPUT NOISE VOLTAGE (nV/ Hz 1000 1000 V+ = 5V AV = 1 100 100 10 0.001 0.01 0.1 1 10 100 1k 10k 100k 10 0.1 1 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 40. CHARACTERIZED INPUT NOISE VOLTAGE DENSITY vs FREQUENCY FIGURE 41. SIMULATED INPUT NOISE VOLTAGE DENSITY vs FREQUENCY 70 60 50 GAIN (dB) 40 30 20 10 0 AV = 1 Rg = OPEN, Rf = 0 100 1k 10k 100k FREQUENCY (Hz) 1M 10M AV = 10 Rg = 10k, Rf = 100k AV = 100 Rg = 1k, Rf = 100k V+ = 5V CL = 3.7pF RL = 100k VOUT = 10mVP-P GAIN (dB) AV = 1000 Rg = 100, Rf = 100k 70 AV = 1000 60 50 AV = 100 40 30 20 10 0 AV = 1 Rg = 10Meg, Rf = 1 100 1k 10k 100k FREQUENCY (Hz) 1M 10M AV = 10 Rg = 1k, Rf = 100k Rg = 10k, Rf = 100k Rg = 100, Rf = 100k -10 10 -10 10 FIGURE 42. CHARACTERIZED FREQUENCY RESPONSE vs CLOSED LOOP GAIN FIGURE 43. SIMULATED FREQUENCY RESPONSE vs CLOSED LOOP GAIN 8 6 NORMALIZED GAIN (dB) 4 2 0 -2 -4 -6 -8 V+ = 5V RL = 100k AV = +1 VOUT = 10mVP-P 1k CL = 824pF CL = 474pF CL = 224pF 8 6 NORMALIZED GAIN (dB) 4 2 0 -2 -4 -6 -8 1M 10M -10 100 1k CL = 824pF CL = 474pF CL = 224pF CL = 104pF CL = 51pF CL = 3.7pF 10k 100k FREQUENCY (Hz) CL = 3.7pF 10k 100k FREQUENCY (Hz) 1M 10M -10 100 FIGURE 44. CHARACTERIZED GAIN vs FREQUENCY vs CL FIGURE 45. SIMULATED GAIN vs FREQUENCY vs CL 14 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 Characterization vs Simulation Results (Continued) 5.0 4.5 4.0 LARGE SIGNAL (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 50 100 150 200 TIME (s 250 300 350 400 V+ = 5V RL = 100k CL = 3.7pF AV = 1 VOUT = 4VP-P LARGE SIGNAL (V) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 50 100 150 200 TIME (s 250 300 350 400 VOUT VIN FIGURE 46. CHARACTERIZED LARGE SIGNAL STEP RESPONSE (4V) FIGURE 47. SIMULATED LARGE SIGNAL STEP RESPONSE (4V) 15 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 SOT-23 Package Family e1 A N 6 4 MDP0038 D SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. F 2/07 NOTES: E1 2 3 E A2 b c 0.20 C 0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D D E E1 e e1 L L1 N 0.15 C A-B 2X C D 1 3 A2 SEATING PLANE 0.10 C NX A1 1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only). (L1) H 6. SOT23-5 version has no center lead (shown as a dashed line). A GAUGE PLANE c L 0 +3 -0 0.25 16 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 Small Outline Transistor Plastic Packages (SC70-5) D P5.049 VIEW C e1 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES MILLIMETERS MIN 0.80 0.00 0.80 0.15 0.15 0.08 0.08 1.85 1.80 1.15 MAX 1.10 0.10 1.00 0.30 0.25 0.22 0.20 2.15 2.40 1.35 6 6 3 3 4 5 0.25 Rev. 3 7/07 NOTES SYMBOL A MIN 0.031 0.000 0.031 0.006 0.006 0.003 0.003 0.073 0.071 0.045 MAX 0.043 0.004 0.039 0.012 0.010 0.009 0.009 0.085 0.094 0.053 5 E 1 2 3 4 C L C L E1 A1 A2 b b1 c c1 C e C L 0.20 (0.008) M C L C b D E E1 A A2 A1 SEATING PLANE -C- e e1 L L1 0.0256 Ref 0.0512 Ref 0.010 0.018 0.017 Ref. 0.006 BSC 0o 5 0.004 0.004 0.010 8o 0.65 Ref 1.30 Ref 0.26 0.46 0.420 Ref. 0.15 BSC 0o 5 0.10 0.15 8o 0.10 (0.004) C L2 WITH PLATING c b b1 c1 N R R1 NOTES: BASE METAL 1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4X 1 R1 R GAUGE PLANE SEATING PLANE L C 4X 1 VIEW C 0.4mm L1 4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. L2 0.75mm 2.1mm 0.65mm TYPICAL RECOMMENDED LAND PATTERN 17 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 Package Outline Drawing L6.1.6x1.6 6 LEAD ULTRA THIN DUAL FLAT NO-LEAD COL PLASTIC PACKAGE (UTDFN COL) Rev 1, 11/07 2X 1.00 1.60 6 PIN 1 INDEX AREA A PIN #1 INDEX AREA 6 B 1 4X 0.50 3 5X 0 . 40 0 . 1 1X 0.5 0.1 1.60 (4X) 0.15 6 TOP VIEW BOTTOM VIEW 4 0.10 M C A B 4 0.25 +0.05 / -0.07 ( 6X 0 . 25 ) SEE DETAIL "X" ( 1X 0 .70 ) 0 . 55 MAX 0.10 C C BASE PLANE (1.4 ) SEATING PLANE 0.08 C SIDE VIEW 0 . 2 REF C ( 5X 0 . 60 ) 0 . 00 MIN. 0 . 05 MAX. ( 4X 0 . 5 ) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 18 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 Mini SO Package Family (MSOP) 0.25 M C A B D N A (N/2)+1 MDP0043 MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL A A1 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. 0.05 0.09 +0.07/-0.08 0.05 0.10 0.15 0.10 Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. E E1 PIN #1 I.D. A2 b c B 1 (N/2) D E E1 e C SEATING PLANE 0.10 C N LEADS b H e L L1 N 0.08 M C A B L1 A c SEE DETAIL "X" 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. A2 GAUGE PLANE L DETAIL X 0.25 A1 3 3 19 FN6560.1 May 29, 2009 ISL28133, ISL28233, ISL28433 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M14.173 14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c MIN 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 14 0o 8o 0o MAX 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS MIN 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 14 8o MAX 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES 9 3 4 6 7 Rev. 2 4/06 e b 0.10(0.004) M C AM BS A1 0.10(0.004) A2 c D E1 e E L N 0.026 BSC 0.65 BSC NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN6560.1 May 29, 2009 |
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